a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device and its manufacture suitable for highly integrated and reliable DRAMs (Dynamic Random Access Memories).
b) Description of the Related Art
As the capacity of DRAM becomes large, it becomes essential to make its fundamental constituent, a memory cell, more finer in order to realize high integration and low cost.
A general DRAM cell is constituted of one MOS transistor and one capacitor. In order to make a memory cell finer, it is therefore substantial that how a large capacitance is obtained from a small cell size.
As a method of procuring a capacitance of a memory cell, a trench type cell and a stack type cell have recently been proposed and adopted as the cell structure of current DRAMs. A trench type cell has a capacitor formed in a trench in the substrate. A stack type cell has a capacitor three-dimensionally stacked above the MOS transistor.
More improved cell structures have also been proposed, particularly for stack type cells, such as a fin type cell and a cylinder type cell. A fin type cell has a plurality of storage electrodes disposed generally in parallel, with the substrate and the upper and lower surfaces of each storage electrode are used as capacitor electrodes so that the capacitance per unit area occupied by a cell can be increased more than a stack type cell. A cylinder type cell has a cylindrical storage electrode disposed generally vertically to the substrate to increase the capacitance.
By using these cell structures and their manufacture processes, it becomes possible to realize DRAMs of 64 Mbit class with 0.35 μm design rule.
However, these technologies only are insufficient for higher integration such as DRAMs of 256 Mbit and 1Gbit class with 0.25 μm to 0.15 μm design rule.
It is therefore necessary not only to reduce a substrate area occupied by a capacitor but to make as small as possible an alignment margin set for eliminating troubles to be caused by wiring shortages or the like during photolithography. It is also necessary to solve the problems associated with improved cell structures such as a cylinder type cell.
A first problem pertains to alignment.
A self align contact (SAC) method is already known as a method of forming a fine contact window. This method is disclosed, for example, in Japanese Patent Laid-open Publication No. 58-115859.
With this method, a first insulating film is formed on a gate electrode layer of a MOS transistor-and patterned to form a gate electrode. After source/drain diffusion regions are formed, a second insulating film Is formed and etched through anisotropic etching until the diffusion regions are exposed. Since an insulating film is formed on the side wall of a gate electrode portion including the first insulating film, the periphery of the gate electrode can be perfectly insulated with the first and second insulating films. Contact window areas can also be formed above the diffusion regions in a self alignment manner.
If the self align method is used for forming contact windows as described above, an alignment margin is not necessary between the underlying conductive layers (gate electrode and source/drain diffusion regions) and contact windows. The cell can be made fine correspondingly because the alignment margin is not necessary. Such a simple self align method is still unsatisfactory because multi-layer processes are used for making highly integrated DRAM cells finer.
An example of improved self align contact techniques used for DRAM cells will be described with reference to schematic cross sectional views of FIG. 34A to 35B which illustrate manufacture processes.
FIGS. 34A and 34B and FIGS. 35A and 35B are cross sectional views of typical memory cell units taken along the direction crossing the word line direction (along the direction of source/drain of MOS transistors). With reference to these drawings, a method of forming contact windows by using the self-align contact technique will be described specifically, the contact windows being used for contact between each of bit lines and storage electrode with the source/drain diffusion region of the MOS transistor.
First, as shown in FIG. 34A, a gate insulating film 113 is formed on a silicon substrate 111 surrounded by a LOCOS oxide film 112. On this gate insulating film 113, a polysilicon layer 114 and a tungsten suicide layer 115 are deposited to form a polycide gate electrode. Source/drain regions 116 are formed on both sides of the gate electrode. A nitride film 117 is formed surrounding the periphery of the polycide gate electrode which corresponds to the word line.
The processes up to this are the same as the above-described self align contact method so that these processes can be executed in accordance with the method described in the Japanese Patent Laid-open Publication No. 58-115859.
Next, a silicon oxide film 118 is formed over the whole surface of the nitride film 117. The silicon oxide film 118 is planarized by chemical mechanical polishing (CMP) or the like to facilitate the succeeding processes.
Next, as shown in FIG. 34B, on the planarized oxide film 118, a resist layer is coated and patterned by usual photolithography to form a resist pattern 119 to be used as an etching mask.
Next, as shown in FIG. 35A, by using the resist pattern 119 as a mask, the oxide film 118 is etched to form contact windows 120 reaching the diffusion regions 116. In this case, the etching conditions of the oxide film is set so as to have a large etching selection ratio of the oxide film to the silicon nitride film. Therefore, even if the nitride film 117 is exposed while etching the oxide film, the nitride film is not etched so much and the areas generally the same as those of the self align contact windows first formed in the nitride film become new contact windows.
Next, the resist pattern 119 is removed by known techniques.
Then, as shown in FIG. 35B, a conductive layer 121 is formed on the contact windows.
With the above method, even if the contact windows are formed above or near the gate electrode because of displacement of the resist pattern 119, the conductive layer 121 and polycide electrode are not electrically short-circuited. Therefore, it is not necessary to have an alignment margin of the contact window relative to the polycide electrode.
According to this technique, contact windows can be formed in a self alignment manner, while planarizing the oxide film 118 serving as an interlayer insulating film.
Such self align contact (SAC) technique will be called hereinafter “nitride film spacer SAC”.
The following problems occur when nitride spacer SAC is used.
One problem associated with the gate electrode structure formed by nitride film spacer SAC is the deteriorated transistor characteristics.
The problems of the gate electrode structure using a nitride film spacer side wall are described, for example, in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 3 MARCH 1991 “Hot-Carrier Injection Suppression Due to the Nitride-Oxide LDD Spacer Structure”, T. Mizumo et. al.
This paper describes that as compared to a MOS transistor with an oxide film side wall, the electrical characteristics of a MOS transistor with a nitride film side wall are deteriorated greatly, for example, in the hot carrier effects, leading to a lower reliability. This may be ascribed to a larger number of traps in a silicon nitride film than in an oxide film.
The above paper discloses a method of preventing deterioration of transistor characteristics by forming an oxide film between the nitride film side wall and gate electrode and between the nitride film side wall and substrate so as to suppress the influence of the nitride film.
However, such a structure cannot be applied directly to the nitride film spacer SAC structure.
This problem will be explained with reference to FIGS. 36A to 37. Similar to FIGS. 34A and 34B and FIGS. 35A and 35B, cross sectional views of typical memory cell units shown in FIGS. 36A, 36B, and 37 are taken along the direction crossing the word line direction. In FIGS. 36A, 36B, and 37, similar elements to those shown in FIGS. 34A and 34B and FIGS. 35A and 35B are represented by using identical reference numerals.
FIG. 36A illustrates the processes corresponding to those of FIG. 34B, and shows a resist pattern 119 on an oxide film 118, which pattern is used for forming contact windows. A silicon nitride-film 122 is formed on a polycide electrode constituted of a silicon film 114 and a silicide film 115, and a silicon nitride film 124 is formed via an oxide film 123 on the side wall of the laminated structure of the polycide electrode and silicon nitride film 122. Impurity doped regions 116 as source/drain diffused regions are formed in the substrate 111 on both sides of the gate electrode.
The resist pattern 119 is formed in order to form contact windows of the nitride film spacer SAC structure. In FIG. 36A, the resist pattern 119 is displaced because of misalignment.
If the oxide film 118 is etched in this state, the side wall oxide film 123 between the nitride film side wall 124 and polycide electrode is also etched at the same time, and the side wall of the gate electrode is exposed, as shown in FIG.36B.
Next, as a wiring electrode 121 is formed in the contact window, as shown in FIG. 37 the gate electrode is electrically shorted to the wiring electrode 121 and diffusion regions 116 via the side wall of the exposed gate electrode.
In order to avoid such electrical short circuits, it is necessary to have an alignment margin and it is impossible to form contact windows in a self alignment manner. The nitride film side wall structure described in the above paper cannot be therefore applied to nitride film spacer SAC.
Another problem associated with nitride film spacer SAC is separation or peel-off of a silicide film to be caused by a combination of a polycide conductive layer and nitride film spacer SAC.
A polycide structure, which is a lamination structure of a silicon film and a silicide film such as tungsten suicide (WSi) and molybdenum silicide (MoSi), has a resistance lower than a silicon film and is widely used for gate electrodes, word lines, bit lines, and the like.
It has been found, however, that if the nitride film spacer SAC process is used with a polycide conductive film, stress is generated because of a difference of thermal expansion coefficient between the polycide film and nitride film and the suicide film can be separated at later heat treatments.
The conventional nitride film spacer SAC cannot be used therefore also for the wiring structure of bit lines or the like, which do not deteriorate transistor performances.
A second problem is associated with a process of forming a contact hole to expose a plug conductive film embedded in another contact window.
For highly integrated DRAM structures, a planarizing process is necessary for preventing breakage or the like of a wiring layer at later processes. For this reason, a structure is adopted which embeds a conductive film called a plug into a contact window.
A process of forming a contact window for contacting a plug with an upper wiring layer is desired to have a process margin relative to the position misalignment. It is also preferable to use SAC in forming a contact window because fine processing is possible.
Under the conditions that an insulating film surrounding a plug can be etched by the contact window forming process, it is not possible to have a process margin relative to the position misalignment and to use SAC. Therefore, a position alignment margin becomes necessary, which hinders high integration.
A third problem is associated with a method of forming a cylinder type storage electrode.
A cylinder type storage electrode utilizes the side wall portion of the cylinder as part of the capacitor of a memory cell. It is therefore necessary to make constant the side wall area of the cylinder in order to stabilize the capacitance.
Generally a cylinder type storage electrode is formed by forming an opening in an insulating film, leaving a conductive layer as the storage electrode only on the side wall and bottom of the opening, and thereafter etching and removing the insulating film.
With these processes, the exposed area of the outer side wall of a cylinder type conductive layer used as the storage electrode changes with an amount of etching the insulating film on the outer side wall of the storage electrode.
A fourth problem is associated with a process of forming a contact window for a conductive layer having a large step.
The structure capable of increasing the area of a storage electrode by using a three-dimensional structure such as a cylinder type cell described above has been studied In order to procure a sufficient capacitance even with a small cell area. A height of the storage electrode is required to be made greater In order to procure a sufficient capacitance. Therefore, a height difference (step) between a cell area and a peripheral circuit area becomes large.
Such a step poses not only a problem of breakage of wiring at the step, but also another problem. Namely, a size accuracy is lowered when wirings over the cell area and peripheral circuit area are patterned, because of an insufficient depth of focus.
There is a method of solving these problems, as disclosed in Japanese Patent Laid-open Publication No. 3-155663, which embeds concaved areas on the surface of an insulating film with a coated insulating film such as spin on glass (SOG) and resist and thereafter etches it back, or planarizes the insulating film formed on uneven cell and peripheral circuit areas through chemical mechanical polishing (CMP).
A problem of a shallow depth of focus can be solved through such planarization. However, following new problems occur.
A DRAM structure has a number of conductive layers which are connected to upper metal wiring layers, including MOS transistor source/drain diffusion regions, word lines, and bit lines respectively in a peripheral circuit area, bit lines, capacitor opposing electrodes, and the like in the memory cell area.
These conductive layers are not formed at the same layer level, but are formed as a multi-layer structure having interlayer insulating films. Therefore, distances of conductive layers from the substrate are different.
If the higher level insulating film is planarized by the above-described processes, the surface of the insulating film is made generally parallel to the substrate surface so that depths of contact holes formed in the insulating film become different.
Therefore, if these contact holes are formed by a single photolithography process, until the lowermost conductive layer—diffusion region—is exposed, the uppermost conductive layer for which contact hole has already formed is exposed in an etching atmosphere for a long time.
An etching selection ratio of the insulating film to the conductive layer cannot be set too high. Therefore, the contact window for the uppermost conductive layer can penetrate into the lower insulating film. At the worst, another conductive layer under the excessively etched contact window can be electrically short-circuited.
In order to form a highly reliable contact hole without electrical short of the lower level wiring layer, it is essential to increase the number of processes, for example, to divide the single photolithography process into a plurality of processes.
A fifth problem is associated with planarization.
DRAM manufacture processes become complicated and the number of processes increases, as the degrees of integration and fine processing become high. These may become a factor of lowering product yields and ultimately raising the cost.
Multi-layer wiring processes are used for high integration. Planarization of insulating layers and wiring layers is therefore important.
Planarizing technology without complicated manufacture processes is therefore desired.
A sixth problem is associated with electrical characteristics of MOS transistors.
As integration becomes higher, MOS transistors are made finer which may cause deteriorated transistor characteristics and lowered reliability.